Turbo Code

Overview

Developed by Efficient Channel Coding, Inc., this library allows users to easily integrate and test various Turbo Product Codes (TPCs) into their SystemVue designs.

Turbo codes are an exciting new class of methods describing the iterative decoding of Forward Error Correction (FEC) codes. Their performance can take error correction within a dB of the Shannon limit for many combinations of code rate and block size. This capability allows turbo codes to replace many Viterbi and Reed-Solomon codes in existing and emerging applications. A number of companies and universities have experimented with turbo codes over the past five years with promising results, but little practical hardware. This changed in late 1998, as Advanced Hardware Architectures Inc. announced Turbo Product Code (TPC) chips developed in conjunction with Efficient Channel Coding, Inc. Efficient Channel Coding has pioneered the development of low complexity, high performance decoding algorithms that Advanced Hardware Architectures has translated to silicon.

The Turbo Code Library V1.0 allows users to easily integrate and test various Turbo Product Codes (TPCs) into their simulations under SystemVue. The tokens feature a rich set of parameters to enable a wide range of code rates, coding gains, block sizes, and latency. Moreover, metric computer tokens are provided to allow interfacing with higher order modulation.

Near term future versions of the Turbo Code Library will support other classes of iterative decoders including Turbo Convolutional Codes (TCCs) for 3G communications systems. A functional simulation of the only commercially available TPC ASIC, the Advanced Hardware Architectures AHA4501 Astro Turbo Product Code Encoder / Decoder, will be available soon as well.

Library Description

The Turbo Code Library V1.0 allows users to easily integrate and test various Turbo Product Codes (TPCs) into their simulations under SystemVue. Future versions of the software will support other classes of iterative decoders including Turbo Convolutional Codes (TCCs). The tokens feature a rich set of parameters to enable a wide range of code rates, coding gains, block sizes, and latency. Moreover, metric computer tokens are provided to allow interfacing with higher order modulation. A functional simulation of the only commercially available TPC ASIC, the Advanced Hardware Architectures AHA4501 Astro Turbo Product Code Encoder / Decoder, is also included.

Token Definitions

Turbo Product Code Encoder Token

• Support constituent codes to 256 bits
• Support block sizes to 65,536 bits
• Two and three dimensional codes
• Helical array encoding for burst error protection

Turbo Product Code Decoder Token

• Support constituent codes to 256 bits
• Support block sizes to 65,536 bits
• Two and three dimensional codes
• Helical array decoding for burst error protection
• Input quantization and clipping level
• Input number representation
• Feedback coefficients on each dimension

Metric Computer Token

This token calculates the Log Likelihood Ratio (LLR) of each bit within a received symbol for optimum decoding. This token must precede the Turbo Product Code decoder if higher order modulations are used.

Demonstration Simulation Systems

BPSK (antipodal modulation) Simulation using the TPC encoder and decoder tokens:

16-QAM Simulation using the TPC encoder and decoder tokens and the metric computer token:

Documentation Support

• Turbo Product Code overview and tutorial
• Helical Encoding Description
• TCL V1.0 Manual : Provides token usage and recommended parameters

Planned Future Upgrades

• Support of Turbo Convolutional Codes (TCCs) including WCDMA and CCSDS
• AHA4501 Turbo Product Code Encoder / Decoder ASIC Emulator
• Support of Concatenated Turbo Product Codes (C-TPCs)
• Support of Turbo Product Coded Modulation (TPCM)
• DSP Code Generators
• Support of future AHA turbo ASIC Products
• Interface to Efficient Channel Coding's AHA4501 Evaluation Board to enable software / hardware co-simulations

Additional Resources

• Turbo Code Library Manual ( 767 KB)
• Turbo Product Code Primer ( 50 KB)
• Helical Interleaver Application Note ( 30 KB)

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