RF System-in-Package/Module - Design Flows

RF System-in-Package/Module Design Flows

The RF SiP designer obtains specifications from the system designer, and evaluates, mix-and-matches (to use best-in-class technology), and optimizes each functional block to meet the system requirements for an optimum performance versus cost.

Algorithm and system level verification tools may be extensively used in this step, especially with ADS Ptolemy, SystemVue and SpectraSys.

The individual chip of multiple ICs may be designed in the RFIC/MMIC design flows with different PDKs or modeled as a behavior model for a faster and higher level simulation.

The designer enters a schematic in ADS for packaging, interconnects, SMT, and embedded passives, and may simulate performance using a variety of frequency domain (linear, non-linear, Circuit Envelope) and time domain (SPICE, synchronous data-flow, timed-synchronous dataflow) simulation technologies. Several of these technologies are patented or proprietary to Agilent. In this step, the RF SiP/Module designer may utilize highly accurate industry standard ADS models, qualified component vendor libraries, and physical component models generated by AMC (Advanced Model Composer) with electro-magnetic simulators to improve the quality of simulations. Once the initial simulation results are satisfactory, the designer can design physical layouts for individual passive components to transform electrical designs to physical designs. Then these components are simulated with EM simulators and verified to the desired component characteristics and values. These components may be stored and re-used for future designs. The full or part of layout may need to be simulated with EM simulators to predict and debug unwanted coupling, parasitic effects, and ground sharing problems. The layout may need to be modified as a result of these simulations.

Also many of design tools, like filter synthesis, facilitate the design process. The critical part of the design, such as embedded passive components and various interconnects, may be simulated with 3D electro-magnetic simulators in ADS to ensure the highest accuracy of simulation results. These designs or simulations may be then co-simulated with Ptolemy.

The layout may need to be modified as a result of these simulations. When the layout is completed, a layout-versus-schematic representation check or DRC can be performed. Layout checking in ADS includes nodal and connectivity checks through the ADS connectivity engine, and DRC completed through ADS DRC engine.

Once the layout is checked it is exported along with applicable drill patterns for manufacturing purposes. Once the part is assembled, performance may be verified using ADS Connected Solutions which performs testing on the part using the same "measurements" used in circuit simulation. This is an effective methodology for custom or proprietary testing where no canned solution exists.

Agilent EEsof supports two design flows, ADS driven RF SiP/Module design flow and ADS Linked RF SiP/Module design flow.

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