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RFIC Design Flows |  |
RFIC design challengesAs RFIC designs have become more complex, the importance of the tools used in their design has grown. Simulation tools must be able to simulate transistor-level circuits with signals corresponding to the latest communication standards. The tools must also have the flexibility to enable designers to simulate arbitrary signals or signals for which the standard is still under development. Preliminary circuit block and system-level simulations with sinusoids are important and are easy to set up. But they are insufficient for verifying the circuits and system will work. What if your circuits and/or system simulations indicate your specifications will not be met? Simulation tools should enable you to figure out where problems are occurring as well as help you determine how to fix them. They must be able to display the results in flexible ways that provide insight, enabling you to make important design decisions. RFIC simulation tools should handle Cadence spectre PDKs directly. RFIC simulation tools should be able to simulate accurately and quickly critical layout elements such as spiral inductors, and easily incorporate the results in higher-level circuit simulations. The simulators should be able to handle extracted views, not just of individual blocks, but of entire transmitters or receivers. They must be able to run Monte Carlo or corner analysis in a reasonable length of time, or designers will skip this important step, risking low yields. They should be able to handle direct-conversion transmitters and receivers with very low frequency signals along with RF, without taking forever. They should be able to handle transient control signals such as those in automatic gain control loops and phase locked loops. RFIC designers should have access to a wealth of simulation examples and technical support, so they can better understand the capabilities of their tools as well as apply them efficiently. Agilent offers the most complete set of simulation tools that satisfy these requirements (and many others) to RFIC designers. Next Section | Generalized RFIC Design Flow Chart RFDE Design Flow Chart | RFIC Dynamic Link Flow Chart | Top of Page Cadence-based RFIC design flowsWithin a Cadence-based RFIC design flow, there are three ways to access Agilent EEsof simulation tools. One is to use GoldenGate, which is accessible as a simulator option within the Cadence Analog Design Environment window. This is the easiest and best solution for designers who are not familiar with Agilent EEsof EDA tools such as ADS and RFDE. GoldenGate is very easy to setup, has a very intuitive user interface, and has extraordinary simulation speed and capacity, especially for simulating large extracted views. The simulation setups and results are stored within the Cadence file structure. You have the option of displaying results using Cadence tools, GoldenGate's qWave, or the ADS data display. Another is to use RF Design Environment (RFDE). RFDE is also intended for RFIC designers who know and like the Cadence simulation environment. It is also available as a simulator option within the Cadence Analog Design Environment. It has many, but not all, of the simulation capabilities of Agilent EEsof EDA's Advanced Design System (ADS). In RFDE, the simulation setups and results are also stored within the Cadence file structure. RFDE Wireless Test Benches enable you to run simulations using "encapsulated" Ptolemy system simulator setups from within the Cadence environment. The third way to access Agilent EEsof simulation tools is by using the RFIC Dynamic Link. Cadence schematics are simulated as subcircuits in ADS, and all ADS simulation tools and capabilities are available. Using the RFIC Dynamic Link is perhaps the preferred method for designers who are familiar with ADS and have simulation setups and data display files that they want to re-use in ADS. (ADS data display files may be reused in RFDE and (with some minor editing) in GoldenGate as well.) RFIC Dynamic Link offers the ability to run co-simulations with Ptolemy from within the ADS environment. Some designers use RFDE for basic simulations and then use RFIC Dynamic Link for the more advanced ones. Previous Section | Next Section GoldenGate design flow: GoldenGate simulation within a Cadence-based RFIC design flowThe greatest advantage of an RFIC design flow using GoldenGate is that it enables you to characterize the performance of your design much more completely than when using other tools. Specifically, it enables the simulation of much larger extracted views, including Monte Carlo or corner analysis simulations of them. This enables you to know whether your design will have a reasonable yield in manufacturing or not. GoldenGate is intended to simulate Cadence schematics with Spectre PDKs directly, without modification. GoldenGate permits early design verification with specification-compliant signals. GoldenGate Design Flow Chart
In this design flow, Cadence is used for schematic capture, with GoldenGate for circuit simulation, accessed via the Cadence Analog Design Environment window. The following types of simulation are available within GoldenGate: DC, AC, S-parameters, transient, harmonic balance, intercept point analysis, gain compression, small-signal noise analysis, and envelope transient. Parameter sweeps, optimizations, and Monte Carlo simulations can also be set up easily and efficiently. Monte Carlo simulations may be run in parallel, hugely decreasing the time required, depending on the number of CPUs available. Layout is carried out normally, using the Cadence tools. Parts of the layout may be simulated using Agilent Momentum, and the results may be re-used in circuit and system simulations by placing a Momentum-generated symbol in a Cadence schematic. Also, the parts of the layout simulated using Momentum may be excluded from the extracted view that is created. This enables the Momentum results to be combined with an extraction of the rest of the circuit in a simulation. GoldenGate Design Flow Chart | RFDE Design Flow Chart | RFIC Dynamic Link Flow Chart RF Design Environment (RFDE) design flow: ADS-based simulation within a Cadence-based RFIC design flow
This design flow is similar to the GoldenGate-based flow described above. An RFIC design flow using RF Design Environment (RFDE) might be preferred by someone very familiar with the ADS simulators. RFDE has a subset of ADS simulation technologies available directly within the Cadence environment. This makes it much easier to know, early in the design process, whether a design will work, and to determine what needs to be improved. RFDE is intended to simulate Cadence schematics using Spectre PDKs, without modification. Simulation setups and results are stored in the Cadence file structure. Results can be displayed using the powerful data display in ADS or translated to Cadence PSF format - or both. ADS simulation technologies permit early design verification with specification-compliant signals, primarily via Wireless Test Benches, - and many more simulation methods than harmonic balance. ADS data display makes it easy to generate complex results such as error vector magnitude (EVM), spectral mask, bit error rate (BER), constellation diagrams, CCDF curves, and other results. The circuit simulators and data display are identical to those found in Advanced Design System (ADS), and in many cases schematics can be simulated without modification. For some types of simulation supported by RFDE but not Cadence Spectre, it will be necessary to edit the schematic to use RFDE-only sources and component models. The following types of simulation are available, all of them with a click of a button in the Analog Design Environment window: DC, AC, S-parameters, transient, harmonic balance, large-signal S-parameters, circuit envelope, and wireless test benches. Parameter sweeps, optimizations, and Monte Carlo simulations can also be set up, also in the same way as would be done using Cadence simulators. Layout. Layout is carried out in the same way as it is normally done, using the Cadence tools. Parts of the layout may be simulated using Agilent Momentum, and the results may be re-used in circuit and system simulations by placing a Momentum-generated symbol in a Cadence schematic. Extracted views are simulated using RFDE, with the setup being the same as when using Cadence simulators. This is done using the config view or by modifying the switch view list. Wireless Test Bench simulation is chosen in the Analog Design Environment window. Input and output nodes must be specified, as well as the results to measure. When the simulation finishes, data display plots showing the measurement results are generated automatically. Previous Section | Next Section GoldenGate Design Flow Chart | RFDE Design Flow Chart | RFIC Dynamic Link Flow Chart RFIC Dynamic Link design flowCadence Subcircuits Simulated in the Advanced Design System (ADS) Environment. When RFIC Dynamic Link is used, Cadence is used for schematic capture of the subcircuits, as is done in the RFDE flow. But simulations are done using Agilent EEsof Advanced Design System (ADS). They are launched from within Cadence, but the design is simulated as Cadence subcircuits placed in ADS schematics for simulation. Everything else about the use of ADS is the same, including access to the complete range of ADS simulation capabilities and tools, including Ptolemy co-simulation. Spectre PDKs can be used, and ADS examples, design guides, and templates can all be used to set up simulations and display results. The simulation setups and results are stored in an ADS project. RFIC Dynamic Link Design Flow Chart
Layout. Layout is carried out in the same way as it is normally done, using the Cadence tools. Parts of the layout may be simulated using Agilent Momentum, and the results may be re-used in circuit and system simulations by placing a Momentum-generated symbol in a Cadence schematic. Extracted views may be simulated, with the subcicuit netlist being generated by either using a config view or by modifying the switch view list. Ptolemy co-simulation is used for verification with specification-compliant signals, and the numerous design library examples may be used as starting points for simulation setups. GoldenGate Design Flow Chart | RFDE Design Flow Chart | RFIC Dynamic Link Flow Chart Request a demoRequest a demonstration of GoldenGate Plus - RFIC Design Solutions. |
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