MMIC Design Challenges
The need for small chips with high performance and low cost has made Monolithic Microwave Integrated Circuits (MMICs) an attractive design solution for many applications. These include cell phones, satellite communications, deep space probes, navigational, weather, and automotive radars, radiometers, and global positioning systems.
All of these applications require high frequency, high bandwidth, and high performance active circuits such as low noise amplifiers, mixers, power amplifiers, oscillators, and switches.
Efficient power use means longer battery life and less weight. Sensitivity and wide dynamic range increase receiver and transmitter range. Linearity supports higher channel density.
In every MMIC design, these and other requirements such as cost and manufacturing yield must be balanced to find the best possible design for the requirements.
Some specific challenges in MMIC design are these:
- Choosing the right device in case of active circuits.
- Minimizing cross coupling and parasitic effects in layout.
- Reducing the die size which is directly proportional to the cost.
- Designing keeping in mind the yield.
- Designing taking into account the packaging of die. (After packaging there is some change in performance.)
- Choosing right package.
- Performance of the circuit should have minimal variation over temperature and bias voltage.
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A Full Front-to-Back MMIC Design Flow
In support of MMIC design, ADS 2008 now features a 100% improvement in design productivity over previous ADS versions, as well as the most capable integrated simulators for performance and yield optimization of MMIC designs. Its many backend design flow enhancements provide designers with a guaranteed error-free integration into their physical design flow and bring a higher level of productivity to the MMIC design process. Some of the major enhancements in ADS 2008 include:
- Automated Trace and Via Insertion
- 3D EMDS that is fully integrated in ADS
- Automatic, Improved DRC and Design Synchronization
- Increased simulation capacity using 64-bit datasets
- Simulated Annealing Optimization
- Improved simulation speed
In addition, ADS physical design tools now fully support integrated reticle generation, as well as external step-and-repeat lithography, with fast import and export in industry-standard GDS II format.
A complete front to back MMIC design solution, all in one single environment.
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Easy Creation of Physical Designs
Regularly updated foundry device models and layouts are always synchronized in both schematic and layout pages. With ADS, it's easy to create physical designs, either by auto-generating a layout from the schematic via design synchronization or by manually placing the layout artwork.
Unlike other vendors with only one mode, ADS features three different synchronization modes between schematic and layout, providing you optimum flexibility in the development of your MMIC. With ADS, you are not constrained by always having your schematic and layout "automatically synchronized," which could mess up the MMIC layout and limits your flexibility. Instead, ADS gives you the flexibility to choose from three different modes of synchronization:
- Single representation with "No Synchronization,"
- Dual representation with "Half Synchronization,"
- Always Automatic Full Design Synchronization between schematic and layout
You can even switch back and forth between the three different modes while you are laying out your MMIC. This flexibility allows you to efficiently and accurately compact your design with more elements into smaller areas. The result is a smaller die size with lower overall cost per chip.
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Powerful LVS Tools
Routing dense lines and elements to fit into a tiny MMIC chip space requires access to good LVS design check tools. In today's highly compacted MMICs, such tools are necessary to be able to successfully design within the tightest area and without re-spins.
ADS features powerful tools to check your layout for errors and ensure that the final layout reflects your schematic design and is correct and error free prior to manufacture. For example, Check Representation offers full functional-node checking to compare schematic and layout for mismatched nodal and parametric values. The Physical Connectivity Engine (PCE) allows you to check your layout, on-the-fly and with a click of a mouse, for any connectivity errors. In addition, a new User Interface tool in ADS 2008 allows you to easily detect and identify any design differences between layout and schematic. Quick action can then be taken to resolve any layout versus schematic differences. As an added benefit, ADS can also export any schematic netlist to use with third-party LVS tools.
A new "Design Differences" window identifies components in layout not in schematic, components in schematic not in layout, parameter differences, and nodal mismatches.
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DRC - Rapid, Automatic Conformance Check
Design Rule Check (DRC) is a simple, foundry-proven method for rapidly and automatically checking layout conformance to foundry process design rules. ADS 2008 features an enhanced version of its DRC tool which allows you to verify that your physical layouts conform to process rules. Now you can find all the errors and their exact "x, y" co-ordinate locations easily. To provide you easy access to fix these errors, they can be sorted according to name or location. ADS DRC rules are now available for most of its major foundries design kits.
An improved Design Rule Checker locates layout errors faster.
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Accurate Interconnect Analysis
Improving interconnect performance and increasing confidence that the manufactured product will function as simulated is crucial in MMIC design. Additionally, there are many types of physical layout components such as high speed connectors, bond wires, and dielectric bricks that require three-dimensional electromagnetic analysis for any arbitrary geometry.
To better address these concerns, the Momentum Planar EM and 3D Electromagnetic Design System (EMDS) simulators are now fully and tightly integrated into ADS 2008, and can easily be accessed in the same design environment. This enables you to verify the proximity effect of chip area compaction, as well as effects of bond wires and packaging, and then to take corrective action on performance and yield early in design process.
The Momentum simulator is the industries' first 64-bit, 3D-Planar EM Solver and now includes a new Krylov Iterative Solver. It hosts three unique solvers to address the varying degrees of EM modeling complexity and extend EM modeling efficiencies across a much wider application coverage area. As a result, you can solve bigger problems, previously not solvable, much faster.
The full-wave and quasi-static solvers and adaptive mesh reduction available with Momentum cover your EM analysis needs from microwave frequencies down to DC. This is especially important to MMIC designers since it allows them to perform very fast design explorations while maintaining accuracy. Momentum also now features improved thick conductor modeling capabilities. Horizontal current modeling on the metal interconnect sidewalls, as well as the vertical currents, have been added for accurate loss or Q calculation at high frequency and shrinking process geometries.
Fast and accurate bond wire drawing with JEDEC industry compliance for EM analysis.
Accurate 3D EMDS simulation and verification of MMIC in package and with bond wires.
The 3D EMDS EM solver integrated into ADS 2008 features an improved 3D viewer and bond wire modeling capability with JEDEC parameter entry. Together with Momentum, it eliminates the need for you to have to leave your design environment to use an EM tool. Rather, with ADS 2008, you can do your full front-to-backend design and EM verification all in one single environment.
After your MMIC is designed, it is packaged and mounted onto a board. Here package effects must be considered in overall design performance. ADS features a unique ability to simulate not only the IC, but also the package and test board as well, so that you can accurately predict in-circuit performance. Momentum RF, a quasi-static EM simulation engine available in ADS 2008 helps ensure accuracy when results are translated to time domain for further analysis. You can now make sure that your MMIC will work 100% after you insert it into its package and after you attach its input and output wire bonds.
A 3D viewer enables you to check your final design layers and connections faster.
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Design Optimal Transient Behavior
In some instances, MMIC requirements have transient response specifications (e.g., VCO startup time and settling time, or amplifier pulsed response). ADS features a Convolution Simulator for transient simulation that allows you to seamlessly access all Frequency Domain Models extracted from Momentum and read them directly into the Convolution time domain simulator. This unique Convolution technology enables you to design optimal transient behavior of your MMIC, while helping you to complete your time domain circuit analysis with high accuracy and first pass success.
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Models and Process Design Kits
Accurate models both for active devices and for passive components are critical in MMIC design. Without accurate models for simulation, it is almost impossible to produce a successful MMIC.
Active Device Models. Active device models can be created using parameter-extraction hardware and software such as Agilent EEsof EDA's IC-CAP. Analytic models can be tested and improved using device measurements.
But by far the most convenient approach is to use foundry-specific process design kits (PDKs). Agilent EEsof EDA has strong relationship with all of the major foundries. All of the Agilent's Process Design Kits are approved, certified, and maintained by these foundries.
PDK support also minimizes simulation problems and errors because the models are designed to work with the simulator. In the Advanced Design System (ADS), the Agilent HBT model is the lead model for HBTs. For FETs, the Angelov (Chalmers), TOM3, TriQuint Materka, EEFET3 / EEHEMT1, Curtice quadratic, Curtice cubic, Materka, Modified Materka, Statz, Tajima, TOM, ADS_FET (for measurement based models) are among the available models used for MMIC design.
ADS MMIC PDKs are complete with electrical and physical models and offer complete front-to-back design support, including design-rule checking (DRC).
Passive Device Models. Models of arbitrary passive structures are often used in foundry kits. Highest accuracy and convenience is produced when these models are based on electromagnetic (EM) simulation and are made available in parameterized in a palette form.
This is the case with Agilent EEsof's Advanced Model Composer, in which a library of multidimensional, fully parameterized, passive planar models for simulating arbitrary-shaped structures can be created. Momentum, the 2.5-D electromagnetic simulator, is run repeatedly to generate these models.
The models provide EM-level accuracy with the speed of an equation-based model. The Model Composer, which is similar to the Advanced Model Composer, may be used for generating EM-based models of common, pre-defined shapes (opens, stubs, tees, bends, gaps, etc.) on custom substrates.
Agilent EEsof EDA provides unique value with Access to Complete MMIC PDKs.
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Simulations
Agilent's Linear simulator for MMIC design includes an extensive set of component libraries, advanced convergence, model generation, and optimization technologies that help to accelerate the overall design process.
Harmonic Balance simulator is used to simulate noise, gain compression, harmonic distortion, oscillator spurs, phase noise, and intermodulation products in non-linear circuits. Agilent's Harmonic Balance simulator is loaded with many advanced features that improve convergence, accelerate simulation and enhance optimization.
Agilent's fast Harmonic Balance simulator is especially useful for the design of the typical nonlinear circuits used in wireless RF and microwave communication systems. It simulates and optimizes the nonlinear steady-state response of amplifiers, multipliers, mixers, oscillators RF system models, and other devices.
Harmonic Balance provides performance measures such as DC bias, mixer noise figure, oscillation frequency and phase noise, large signal S-parameters, and power added efficiency. Agilent's simulator also provides swept variable (for example, power, frequency or circuit parameter) analysis, parametric subnetworks, and large-signal S-parameters.
Transient-Assisted Harmonic Balance (TaHB) is an advanced technology which was created specifically for addressing the challenges of designing highly non-linear circuits. The simulator runs transient analysis first and uses its results as an initial condition for harmonic balance to complete the solution. This process is fully automated process is easy to use and results in faster simulation and convergence of highly non-linear circuits.
Noise analysis of non-linear circuits is another area where the HB is very effective. HB, with its nonlinear frequency-domain technique, easily lends itself to the fast and accurate noise analysis of mixers and oscillators while including large-signal effects.
Designers can optimize mixer noise performance by looking at the effects of various different DC bias or LO levels on oscillator phase noise, on noise figure of frequency translation circuits such as mixers and receivers, and on bit error rates (BER).
The design performance can also be verified with the use of ADS system simulator (Ptolemy) by means of Co-simulation. For example, an amplifier could have an EVM spec that should be met with some kind of a wireless modulated signal. This can be done easily by co-simulating it with Ptolemy which provides many of the wireless standards signals.
Agilent EEsof EDA provides unique value with True Circuit Verification to all Wireless Standards.
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Optimization, Yield, and Statistical Design
A successful design not only meets specifications in the ideal case, using nominal values. The design has also been optimized for high manufacturing yield in production.
Statistical design and analysis tools can significantly improve overall production yield. Components that have the largest effect on yield can be identified and the topology revised to minimize the impact of process variations in manufacturing.
Specifications can also be revised or tightened, especially for purchased parts that, in manufacturing, have a large effect on yield.
Statistical Design Steps
Statistical design for MMIC designs typically consists of the following steps:
- Generate a first-cut design for simulation.
- Optimize the design to meet the electrical specifications.
- Perform a yield analysis based on the known effects of variations due to the manufacturing process.
- Generate yield sensitivity histograms to identify the components or process parameters that have the greatest negative effect on manufacturing yield. These are often called Red X components and parameters.
- Perform design-of-experiments (DOE) analysis, to replace the most sensitive design topologies with less sensitive topologies, thereby increasing manufacturing yield.
- Perform yield optimization (sometimes called design centering) to choose the values for manufacturing that give the highest yield of devices that meet the electrical specifications.
Example: MMIC Design Enhancements Using Statistical Design Tools
Online Demos: Statistical Design in ADS
Agilent EEsof EDA provides unique value in Achieving First Pass Success and High Yield.
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Layout/Physical Design
The layout and schematic are synchronized and the layout changes as the schematic changes.
From the Layout mode, the designer can access Momentum EM simulator to accurately model structures that help producing more accurate designs.
Momentum Physical Verification. Agilent Momentum 3D planar EM simulation offers 64-bit support with advanced meshing and solver technologies that enable simulation even of thick metal layers and curved traces that are difficult to mesh with traditional square "Manhattan" meshing.
Physical structures such as inductors, MIM capacitors, and traces can be simulated and optimized in both the schematic and the layout environments, and EM simulation results can be used in system-level simulations without the need for translation or file transfers using third-party tools.
Online Demo: Layout Cosimulation
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Layout Verification and Output
When the layout is complete, a check on the layout can be run, a layout-versus-schematic (LVS) check with third-party tools can be performed, and a Design Rule check is done before going into fabrication.
The layout is then exported to the format that is used by the foundry: GDSII, Gerber, DXF, and others.
The wafer is then fabricated, tested, and diced into small chips that are then packaged and assembled on board. The packaged chips are then tested. When Agilent EEsof EDA's connected solutions are used, the test signals can be wireless standard modulated signals that are produced from a system simulator such as Agilent Ptolemy.
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