Agilent EEsof EDA Events

2008 High-Speed Digital Seminar - Tackling High-Speed Serial Designs

Overview:

Today´s digital designs feature high-speed serial I/O technology like PCI EXPRESS®, Fibre Channel, SATA, etc., with data rates >2.5 Gb/s, embedded clocks, differential signaling, and layout density that makes probing difficult. Knowing how the latest tools can accelerate the design and validation process helps you get your products to market faster. At this event, you’ll learn about recent breakthroughs in test technology that enable designers to tackle their greatest high-speed digital design and validation challenges more efficiently and effectively than ever before.

What to expect:

You are invited to this complimentary full-day seminar, where you will see the latest high-speed digital, signal integrity, and jitter analysis innovations focusing on both design and validation solutions from Agilent Technologies. You will learn about the most advanced applications, solutions, and technologies in high-speed digital areas such as signal validation of high-speed interconnects/buses, jitter analysis of digital signals, physical-layer measurements of components and backplanes, and protocol analysis. Unique solutions will be discussed along with approaches that support the higher data rates of future implementations.

Who should attend:

This seminar will be valuable to engineers in a number of industries where new high-speed memory, I/O, or communications technologies are being implemented.

Agenda:

• 8:00 am - 8:30 am Registration & Continental Breakfast
• 8:30 am – 9:00 am Kickoff “Tackling High-Speed Serial Designs”
• 9:00 am – 10:00 am How to Solve DDR Parametric and Protocol Measurement Challenges
• 10:00 am – 10:15 am Break/Demo Fair
• 10:15 am – 11:15 am Successfully Negotiating The PCI Express 2.0 Super Highway Towards Full Compliance
• 11:15 am – 12:15 pm Characterizing Your PLL-based Designs To Manage System Jitte
• 12:15 pm – 1:15 pm Complimentary Lunch/Demo Fair
• 1:15 pm – 2:15 pm Modeling Multi-Gigabit FPGA Channels Using ADS
• 2:15 pm – 3:15 pm TDR, S-Parameters & Differential Measurements
• 3:15 pm – 4:15 pm A Design of Experiments for Gigabit Serial Backplane Channels
• 4:15 pm – 4:45 pm Demo Fair

Locations:

• Sept. 16, 2008 ........ Santa Clara, CA
• Sept. 23, 2008 ........ Austin, TX
• Sept. 25, 2008 ........ Richardson, TX
• Sept. 30, 2008 ........ Melbourne, FL
• Oct. 15, 2008 ......... Thornhill, ON
• Oct. 17, 2008 ......... Ottawa, ON

Topics:

Tackling High-Speed Serial Designs   The demand for more system bandwidth has driven the design of several new protocol-rich high-speed serial interconnect standards. Today´s challenge is incorporating 2.5 to 5.0 Gb/s data rates in designs like PCI EXPRESS®, SATA, FBD, and DisplayPort, with 6 to 10 Gb/s variation coming. This presentation will discuss the important factors in characterizing the physical layer of differential serial interconnects such as minimizing reflections with quality impedance design, minimizing jitter effects, utilizing new compliance tools, and more.

How to Solve DDR Parametric and Protocol Measurement Challenges   DDR memory technology which is essentially parallel bus technology is reaching the speeds of serial technology. As the speed increases, the validation effort increases exponentially. The parametric and protocol performance has to be validated in order for the memory system to function properly. They are the key to system interoperability, or the guarantee that devices from different vendors will integrate well. This presentation outlines the validation challenges that many customers face today, describes some of the new probing solutions and tools for DDR parametric and protocol validation that will overcome some of the challenges.

Successfully Negotiating The PCI EXPRESS® 2.0 Super Highway Towards Full Compliance   PCI EXPRESS® 2.0 operates at twice the data rate (5.0 Gb/s) compared to PCI EXPRESS® 1.x technology. Significant changes in physical layer electrical measurements, and link and transaction layer compliance tests were implemented. This presentation review these changes, how to validate your motherboard and add-in card device under the 2.0 spec helping to ensure that you will be ready to qualify for the Integrator’s List. In addition, you’ll learn about how to ensure your designs are taking maximum advantage of the upgraded throughput offered by PCI EXPRESS® 2.0.

Characterizing Your PLL-based Designs To Manage System Jitter    Although data rates for next generation serial busses typically double the information capacity of the previous generation, costs are not allowed to double. Use of low-cost components, specifically reference clocks and integrated VCO’s, place significant burdens on the PLL and DLL circuitry in system transmitters and receivers. Knowing and understanding the effects of the PLL and clock recovery circuits is key to controlling jitter performance. This presentation will examine how the design and performance of the various elements of a system (clocks, PLL’s, DLL’s etc.) interact with each other and eventually lead to an overall system jitter budget. PLL and high-precision jitter measurement techniques will be discussed in detail.

Modeling Multi-Gigabit FPGA Channels Using ADS   This paper will model real world circuit boards using S-parameters, showing that it is possible to predict eye opening performance before a system is physically prototyped. Both extracted and measured models for the interconnect will be used. A 90nm transceiver model is incorporated in ADS as a new library element, permitting system level modeling of interconnects and FPGA transceivers. Both measured and modeled results are shown and the correlation is discussed, concluding that the new method is both execution time efficient and is sufficiently accurate to provide a high level of confidence for designers wishing to design serial links to 6.375 Gb/s. Presented in cooperation with Altera Corp.

TDR, S-Parameters & Differential Measurements   With the increase in speed of digital system design into the gigahertz region, frequency dependent effects become a more prominent challenge than in the past. The proliferation of high speed serial data formats in today’s digital standards demand differential circuit topology. A paradigm shift in measurement technology is required to achieve the design goals of the advanced differential physical layer. It is now necessary to consider both time and frequency domain analysis to obtain proper characterization. This presentation reviews TDR, S-Parameters, and Differential measurements using a TDR.

A Design of Experiments for Gigabit Serial Backplane Channels   Today´s backplane environment presents significant challenges for high-speed digital designers. Tradeoffs between signal integrity performance, cost, and reliability must be made to achieve the proper architecture for a robust physical-layer channel. The right combination of connectors, dielectric materials, and topology must be used to accomplish this engineering task. This paper will discuss an in-depth design of experiments using combinations of three high-speed connectors, three dielectric materials, and three channel lengths. Data will be gathered with a 12-port vector network analyzer and the results will be presented in time domain, frequency domain, and eye diagram domain. Presented in cooperation with Xilinx Inc.

PCI EXPRESS is a registered trademark of the PCI-SIG.

Registration:

Seating is limited for this complimentary full-day seminar and early registration is advised. You will receive an e-mail confirming your registration and web link with directions to the seminar location.

Click the following link for more details and information on how to register for this event.

• 2008 High-Speed Digital Seminar - Tackling High-Speed Serial Designs, September 16^th through October 17^th 2008, multiple cities

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Interconnect Analysis & Modeling Workshop

Why this workshop is important:

Today´s digital designs feature high-speed serial I/O technology like PCI EXPRESS®, Fibre Channel, SATA, etc., with data rates >2.5 Gb/s, embedded clocks, differential signaling, and layout density that makes probing difficult. High-frequency effects from interconnects - traces, vias, connectors, cables, etc. - can significantly impact your design. Knowing how to use the latest tools can accelerate the design and validation process to help you get your products to market faster. At this event, you´ll learn about key test and simulation tools that enable designers to include interconnect effects in their simulations to predict how their design performs before building it.

What to expect:

To be successful in creating designs with today’s high-speed data rate serial standards, you need to include the effects of impedance in your design simulations. These include chip-to-chip interconnects on the board, vias, connectors, cables, and backplanes. This requires the designer to combine the digital and RF effects in an analog simulator that includes interconnect models. This workshop will illustrate how to make interconnect measurements, create interconnect models, incorporate them in simulations, and how to use the simulations to better understand your design. The workshop combines lecture and hands-on labs with Agilent experts using a real backplane as the test device to illustrate the techniques involved. These Agilent technical experts and application engineers will also be available for informal discussions about your unique application.

Who should attend:

This workshop will be valuable to engineers in industries where new high-speed memory, I/O, or communications technologies are being implemented and data rates exceed 2 Gb/s. No experience with frequency domain measurements, S-parameters, Vector Network Analyzers (VNA), Physical Layer Test System (PLTS), or EEsof Advanced Design System (ADS) software is required.

Agenda:

The workshop will start with a presentation reviewing the measurement and simulation technologies, approaches, case studies and resources available. Attendees will then break into two groups and start the first lab, then swap. The hands-on labs are:

• Measurement Lab:
  Review a TDR and VNA, discuss TDR and VNA calibration techniques, perform a multi-port calibration, review PLTS automation capabilities, make differential measurements, interpret time and frequency domain results, understand differential S-parameters, and create data file for ADS use.
• Simulation Lab:
  Review ADS environment, incorporate measured data in a circuit, perform a circuit simulation, interpret simulation results, review "scope” display mode, create an equivalent circuit model for backplane, optimize model to match measured results, explore what-ifs, and review advanced ADS features.

The workshop is given either as a morning session or an afternoon session. Please select which session you plan to attend.

Registration:

Seating is limited for this complimentary half-day workshop and early registration is advised. You will receive an e-mail confirming your registration and web link with directions to the seminar location.. Click the following link for more details and information on how to register for this event.

• Interconnect Analysis & Modeling Workshop, 22 September 2008, Santa Clara, CA

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Helping you build your business – fuelling early stage technology growth forum

Why this even is important:

Whether you are an early-stage business or in the process of starting up, we understand the challenges you face with the limited resources, stringent milestones and no revenue stream; as well as a finite amount of funding. The good news is we can help you to get off to a good start and have designed a forum to help you address the issues specifically related to starting up in today's market!

Designed to help you build your business, you'll hear from the UK's most dynamic early-stage technology businesses, from companies in their infancy to companies who have successfully worked through the challenges you face in the early days. You will learn how to get soft access to assets without adding cash burden to grow your business.

Benefits of Attending:

• Hear from business experts who have started some of the UK's best start up companies
• Learn from guest speakers and take away practical tips to help you develop your business
• Identify new market trends and leverage new technologies to achieve a competitive advantage
• Learn techniques that will save money, speed up growth and preserve cash
• Understand best practice - find out how other companies have grown faster or reduced time to market
• Network with your peers and make valuable new business contacts

Who should attend:

This forum will benefit CEO’s, CFO’s, CTO’s, Senior Managers, VP of Engineering functions, Innovators and like minded business entrepreneurs, investors and business experts.

What to expect:

Jointly Sponsored by:

• Agilent Technologies
• Microrelease
• Cambridge Wireless

Learn how we can support your business by providing the tools, resources and knowledge you need to meet “time to market” needs in our rapidly changing environment.

• Access to market leading test solutions combined with an extensive network of factory expertise enable you to optimise your product development cycles to achieve a competitive advantage.
• To keep your costs to a minimum we have partnered with Microlease plc, Agilent’s European Premier Rental Partner to offer flexible financial solutions help you make efficient use of funding to minimise “burn rate” and lower the cost of ownership.
• And with our market leading industry experience, we can also help you generate positive exposure through communications, all designed to help you get your business off to a good start.

Agenda:

Registration:

Agilent Technologies, Microlease and Cambridge Wireless will share registration information.

Click the following link for more details and information on how to register for this event.

• Unitked Kingdom Landing Page: Helping you build your business – fuelling early stage technology growth forum, 24 September 2008, Cambridge, UK
• Ireland Landing Page: Helping you build your business – fuelling early stage technology growth forum, 24 September 2008, Cambridge, UK

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Tradeshow: Antenna Systems Conference 2008

Overview:

The 2008 Antenna Systems Conference will take place September 25-26 at the Hyatt Regency Austin in Austin, Texas. It is a two-day international conference focused on the latest and most important advancements in antenna systems and technology.

EEsof EDA is exhibiting and presenting at this event.

Day 2, Friday, September 26^th 2008

1:15 pm
Advances in Antenna Design For Circuit Designers by Erwin de Baetselier
Designers today need an EDA toolset that helps them cope with the challenges of high frequency, highly integrated and highly outsourced design work. High frequency and small scale integration are causing signal integrity problems. This implies the need to simulate the Electromagnetic effects of 3D elements such as bondwires and dielectric bricks together with the circuit. Increased outsourcing, as we see in the wireless appliance industry, has seriously increased quality risks. This presentation will show how those can be reduced if the various components such as the antenna, the circuit and the human manipulation are simulated in the same environment.

For more information:

Click the following link to view the entire Antenna Systems Conference 2008 Program (PDF)

• Tradeshow: Antenna Systems Conference 2008, 25—26 September 2008, Austin, TX

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Genesys European Learning Week

Overview:

Offered over the course of three days, starting on October 15th will be a continuous series of training classes with hands-on labs covering a wide range of topics about the Genesys RF-Microwave Design Software.

Agenda:

• Day 1: 7am—3pm GMT
• Genesys Basics
• Filter Synthesis, Layout, and Empower
• Libraries, Parts, and Models
• Day 2: 7am—3pm GMT
• Linear Analysis, Sweeps, and Optimization
• Non-linear Analysis and Design
• Synthesis for Mixers and Oscillators
• Day 3: 7am—3pm GMT
• WhatIf
• Spectrasys Basics
• Spectrasys Applications

Registration:

Click the following link for more details and information on how to register for this event.

• Genesys European Learning Week, October 15—17, 2008 Massy, FRANCE (Microsoft Word Document, 211KB)

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Tradeshow: RF&Hyper 2008

Overview:

RF&Hyper is dedicated to radiofrequencies, microwaves, wireless, optical fibres and their applications.

EEsof EDA is exhibiting at this event.

For more information:

Click the following link for more details about this event.

• RF&Hyper 2008, 30 September — 02 October 2008, Paris, France

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Tradeshow: Jazz Annual Technology Conference

Overview:

This year's conference series is focused on the central theme of "Analog Technology Convergence Creates New Opportunities for Innovation." The event will include a list of key invited speakers as well as contributed talks, vendor exhibits, and a cocktail reception hosted by Jazz. All participants will have an opportunity to meet with top executives and technical professionals as well as key technical and management professionals in the semiconductor industry.

All attendees and presenters are encouraged to attend JATC the following day, October 23rd at Jazz Headquarters. There will be a formal exhibition area open on both days (October 22-23) where all attendees will be able to experience the latest from tool and IP providers, design companies, and post wafers service companies.

EEsof EDA is exhibiting at this event.

For more information:

Click the following link for more details about this event.

• Jazz Annual Technology Conference, 22—23 October 2008, Newport Beach, CA

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Tradeshow: SDR Forum

Overview:

SDR'07 featured more than 130 papers focusing on software defined and cognitive radio technologies, standards, regulatory issues and business activities - presented by an international array of researchers and organizations in the commercial, civil and defense communications markets to attendees from over 15 countries.

EEsof EDA is exhibiting at this event.

For more information:

Click the following link for more details about this event.

• SDR Forum, 26—30 October 2008, Washington, D.C.

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Tradeshow: Electrical Performance of Electronic Packaging (EPEP 2008)

Overview:

The 17th Topical Meeting on Electrical Performance of Electronic Packaging will be held October 27-29, 2008, in San Jose, California. The 2007 meeting attracted a large number of professionals to what is now widely recognized as the premier technical meeting on electrical considerations in packaging.

EEsof EDA is exhibiting at this event.

For more information:

Click the following link for more details about this event.

• Electrical Performance of Electronic Packaging, 27—29 October 2008, San Jose, CA

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Tradeshow: European Microwave Week, EuMW 2008

Overview:

The European Microwave week provides the opportunity to attend these four conferences, and various workshops and short courses given by leading experts in their field. Moreover, the European Microwave Exhibition constitutes the largest trade show on RF and microwaves in Europe.

This week, Agilent offers various complimentary workshops and tutorials.

For more information and registration details, please select:

• Agilent Technologies Workshops
• Agilent Technologies Tutorials

EEsof EDA will be presenting the following papers:

Day 1, Tuesday, October 28^th, 2008

09:30 — 10:50
LTE - From Concepts to Simulation to RF Design and Troubleshooting
To ensure the competitiveness of 3G systems into the future, a long-term evolution (LTE) of the 3rd Generation Partnership Project’s (3GPP) UMTS is being defined. This workshop will cover the timeline behind LTE, a context provided to position it against the alternative 3.9G technologies such as HSPA+ and WiMAX™. There will be a brief introduction to the new OFDM air interface and more detail on the new uplink transmission scheme, SC-FDMA. The paper will give an overview of the physical layer frame structure. The paper will then go into a discussion on design flow from concept-to-test for 3GPP Long Term Evolution (LTE). An algorithm development methodology will be shown for coding key algorithms in the LTE coding/decoding chain. Baseband algorithms are then combined with the RF system design to examine various system level trade-offs, including the effects of baseband bit width, phase noise, and power amplifier non-linearities on key system performance metrics such as Error Vector Magnitude (EVM). Uncoded raw Bit Error Rate (BER) will also be investigated.

15:30 — 17:00
Adaptive Antenna Tuning for efficient design of handheld wireless appliances
Antenna Designers today, are put under pressure of the Network Operators to improve the performance of the antenna systems under all operating conditions. Some network providers are willing to pay an increased value of $2 per handset for a 2dB improvement of the antenna system. To reach that goal, designers need an EDA toolset that helps them cope with the challenges of high frequency, highly integrated and at the same time highly outsourced design work. Increased outsourcing as we see in the Wireless appliance industry has seriously increased quality risks. Those can be reduced if the various components such as the antenna, the circuit and the human manipulation are simulated and optimized in the same environment. We will show how the ADS RF design front-end platform is used for EM, system and circuit co-simulation to optimize an adaptive tuning mechanism for antennas inside a wireless appliance during human manipulation optimization will be highlighted as well.

Day 2, Wednesday, October 29^th, 2008

11:00 — 12:20
X-Parameters: New Paradigm for Interoperable Measurement, Modeling, and Simulation of Nonlinear Microwave and RF Components
X-parameters are the mathematically rigorous superset of S-parameters, applicable to nonlinear (and linear) components under both large-signal and small-signal conditions. X-parameters take into account mismatch at fundamental and harmonic frequencies, and correctly predict effects of source harmonics on DUT response. X-parameters enable the hierarchical design of chains of nonlinear components under large-signal drive, such as multi-stage power amplifiers, multi-chip RF modules, and RF systems including amplifiers and mixers. X-parameters measured by Agilent’s new nonlinear vector network analyzer (NVNA) can be used, immediately, in Agilent ADS, to design nonlinear circuits. The ability to measure, model, and simulate with X-parameters, is a big step towards doing for nonlinear components and systems, what S-parameters do for linear components and systems. This paper introduces X-parameter theory and a few key examples of its applications, including its superiority to “hot S22” in accounting for output match of amplifiers under large-signal drive.

Day 3, Thursday, October 30^th, 2008

14:00 — 15:00
Design and analysis of a 2.4GHz polarization diversity printed dipole antenna with integrated balun and polarization switching circuit for WLAN applications using Momentum and EMDS-for-ADS
In this seminar application note we will take you through a complete design process to design and analysis of a 2.4GHz polarization diversity printed dipole antenna with integrated balun and polarization switching circuit for WLAN applications using ADS. Special attention will be given to the effective use of Momentum and EMDS-for ADS for electromagnetic modeling. The use of layout, circuit modeling simulation, EM optimization will be highlighted as well.

15:15 — 16:15
High Yield MMIC Front-To-Back Design with ADS 2008
The art of designing MMICs to satisfy speed to market at the lowest cost is attainable with robust design methodology implemented within a productive design environment. This paper shows you how to take advantage of the latest productivity enhancements in ADS 2008 to accomplish this. Beginning from selecting a process design kit from the widest choice of MMIC foundries in a high-frequency EDA tool, you start your journey in this optimal MMIC design flow. Tightly integrated circuit, statistical, electromagnetic and system simulations are used in turn to efficiently optimize the performance, yield and wireless standards compliance of your MMIC within a fun-to-use design environment.

For more information:

Click the following link to view the entire EuMW program. (PDF)

• European Microwave Week 2008, 28㬚 October 2008, Amsterdam, The Netherlands

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Tradeshow: MILCOM

Overview:

Now in it’s 27th year, MILCOM has established itself as the premier international conference for military communications, attracting decision-makers from government, military, academia, and industry. The conference also gathers the brightest military and government communications subject matter experts from around the globe to engage in in-depth discussions about the latest in technology advancements. This makes MILCOM an ideal forum for industry to demonstrate how these technologies are being applied, and to promote products and services that provide reliable solutions to today’s mission-critical challenges.

EEsof EDA is exhibiting at this event.

For more information:

Click the following link for more details about this event.

• MILCOM, 17—19 November 2008, San Diego, CA

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Advanced Design System European Learning Week

Overview:

Join us for the 2008 ADS Learning Week in Munich starting on Monday November 24th, 2008! Over the course of the entire week we will offer a continuous series of training classes covering a wide range of topics about ADS Circuit, EM and Signal Integrity.

The schedule is modular and consists of two separate tracks (one for EM Simulation, the other for Circuit Simulation and Signal Integrity), allowing you to choose any combination of topics. You can register for one or more days at your convenience. These classes cover a wide selection of material used in the popular Agilent EEsof Customer Education classes and will be led by qualified Agilent Instructors. Computers will be provided by Agilent for those who do not plan to bring their own laptop.

Agenda:

Registration:

Click the following link for more details and information on how to register for this event.

• Advanced Design System European Learning Week, November 24—28, 2008 Munich, Germany

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Weekly Live Genesys and SystemVue Demos

Live Genesys Demos!

Join us via WebEx and a telephone conference on Thursdays at 10 a.m. PDT/1 p.m. EDT for one hour.

Topics will include an overview of the latest Genesys version and a look at new modules.

Interactive SystemVue Demos!

Join us via WebEx and a telephone conference on Thursdays at 10:30 a.m. PDT/1:30 p.m. EDT for one hour.

Topics will include an introduction to SystemVue and application-specific examples.

For either of these events . . .

If you are west of the Mississippi River, call Walt Best at (866) 462-4662 or email salesuswest@wlv.agilent.com. If you are east of the Mississippi, call Paul Beavin at (866) 581-0484 or email salesuseast@wlv.agilent.com.

They will follow up with the WebEx and telephone conference information.

We look forward to seeing you at the WebEx!

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