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Advanced RFIC Design Techniques Seminar: Downloads

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Advanced RFIC Design Techniques Seminar

Advanced RFIC Design Techniques is a complimentary one-day seminar presented by Agilent Technologies in alliance with Cadence Design Systems and co-sponsored by Electronic Design and Wireless System Design. It was presented in the United States and Canada during the month of September 2002 and worldwide during the months of November and December 2002.

This page offers abstracts and downloadable versions of the technical presentations and of the seminar flyer.

Technical Presentations

System-Level Solutions: A Tops Down Approach to IC Design - Frank Ditore and
Kal Kalbasi.
Download PDF (989 KB). 37-page slide presentation with speaker's notes.   ADS Project Files.

Traditional design flows, where individual blocks are designed based on isolated system partitioning, are only effective for smaller and less complex designs. As the trend for more functionality in fewer chips with lower power and cost continues, designers face the need for an improved, tops-down design methodology that offers efficient partitioning at the system level for both RFIC and IF/BB functionality.

This paper traces the design flow associated with a sample communications system, with emphasis on receiver design. This design is intentionally generic to show the generality of the methodology for a wide range of applications with a common RF/Mixed-Signal focus.

Phase-Locked Loop Design - Analysis of a Sigma-Delta Modulator Using RF Behavioral Modeling and System Simulation - Andy Howard.
Download PDF (869 KB). 45-page slide presentation with speaker's notes.   ADS Project Files.

Often it is desirable to create a phase-locked loop with frequency resolution finer than the reference oscillator frequency. This presentation covers basic phase-locked loop operation, fractional-N PLL simulation (which generates spurs) and sigma-delta PLL simulation to eliminate spurs.

The simulations are carried out at the behavioral-model level, using Agilent Ptolemy to model the sigma-delta modulator components and Circuit Envelope to model the PLL components, all at the behavioral level. A technique for including VCO phase noise in the simulation also is demonstrated.

Verification of a Power Amplifier Design in a WLAN System Based on a Connected Simulation and Test Environment - Joe Troychak.
Download PDF (3.2 MB). 40-page slide presentation with speaker's notes.   ADS Project Files.

Wireless networking radio designers are rapidly developing and testing new products based on the IEEE 802.11a/b/g wireless LAN (WLAN) and Bluetooth standards. Simulation and verification tools are essential for ensuring specification compliance with each standard, both for IC-level baseband and RF circuits, as well as for system-level reference designs.

Design and verification tools must accurately generate and analyze complex modulated signals to validate prototypes early enough to meet shortened design cycles and extremely low price targets. By integrating circuit- and system-level design environments with test instrumentation, common analysis and verification algorithms are used to standardize design flows and verification methodologies.

Recent Design Advances for RF/Mixed-Signal IC Development - Cadence
Design Systems.
Download PDF (1.80 MB). 24-page slide presentation.

This presentation discusses new capabilities and performance enhancements available in the Cadence IC5.0 release. These capabilities contribute to new abilities in the RF MS IC design flow including new analyses, measurement capabilities and modeling. Also discussed is Cadence's Linux platform support and OpenAccess roadmap leading to higher performance and capacity for next generation nanometer and RF MS designs.

Efficient Analysis and Simulation of a Direct Conversion I-Q Modulator - Jack Sifri.
Download PDF (3.3 MB). 60-page slide presentation with speaker's notes.

This paper covers the efficient analysis of a direct-conversion, in-phase/quadrature transistor-level I-Q modulator utilizing frequency- and mixed-domain simulation technology. Included in the modulator are differential-mode mixers, a combiner, a buffer, and a power amplifier.

This modulator design is used to demonstrate the many simulation capabilities required to adequately evaluate the performance of an I-Q modulator. Simulations of each of the modulators sub-circuits are also included. Amplifier gain compression, load pull, AC frequency response, mixer intermodulation distortion as a function of various swept parameters, modulator amplitude and phase accuracy, and simulations with CDMA baseband data sources are simulated and analyzed.

ADS Project Files

ADS Project Files: System-Level Solutions: A Tops Down Approach to IC Design

This ADS project consists of the following designs. Each design has associated data displays with the same name.

NOTE. All of the datasets in this project have been deleted, to keep the .zap file size as small as possible. After the project file has been downloaded and opened, re-simulate each design to see the results.

DQPSK_Timed_BER_Bench.dsn. This design contains a high-level simulation of a DQPSK modem using timed components found in the ADS Ptolemy library. BER results are simulated in this project.

DQPSK_Numeric_Modem_Test.dsn. This design contains a purely numeric simulation of the DQPSK modulator and decoder, including the bit slicer. Modulated and demodulated constellations are simulated along with decoded data.

DQPSK_RF_Modem_Test.dsn. This design is a BER template for simulating the performance of the floating point numeric DQPSK decoder and bit slicer. BER is simulated along with modulated and demodulated constellations and power spectrums.

DQPSK_RF_Modem_Test_FPDEMOD.dsn. This design is a BER template for the fixed point implementation of the DQPSK decoder with floating point bit slicer. BER is simulated along with modulated and demodulated constellations and power spectrums. Two parameter sweep controllers allow you to vary fixed point bit width along with the simulated Eb/No.

DQPSK_RF_Modem_Final_Link_Test.dsn. This is a BER template that includes a high level Ptolemy model for the LNB (includes LNA, Mixer, LO, Filter) along with the fixed point DQPSK decoder and floating point bit slicer. Effects of NF with fixed point impairments are simulated. BER is simulated along with modulated and demodulated constellations and power spectrums.

DQPSK_RF_Modem_Final_Link_Test_Superhet.dsn. This is the final BER template that includes a circuit level block/device level model of a superhet receiver RF/IF architecture along with the fixed point DQPSK decoder and floating point bit slicer. This is the final verification of the system.

Also included in this project is a data display titled Link_Analysis.dds that allows you to perform simple calculation of link budget.

ADS Project Files: Verification of a Power Amplifier Design in a WLAN System

Except for the fast co-simulation design WLAN_PA_fast_cosim.dsn these two .zap format project files are the same, and contain all of the following designs. The fast co-simulation design is included only in the ADS 2002C version of the project file.

All of these designs default to a carrier frequency of 2 GHz.

WLAN_PA_swp.dsn sweeps the WLAN signal source data rate parameter.

With this design, the VSA auto-detects each new modulation type for acquisition after the rate changes. The VSA displays modulation changes as a function of swept rates.

Note that you must quit the TkSlider display each time to change rates, a "feature" of swept interactive displays.

WLAN_PA_burst.dsn displays VSA spectral and time domain plots without demodulation.

For use with this design, the VSA setup CCDF.set shows the setup for CCDF simulations. Pause the VSA to see the leading/trailing edges, or record/playback.

WLAN_PA.dsn shows the nonlinear power amplifier simulation at variable WLAN signal source data rates.

In this design, change the data rate using the Rate parameter in variable block VAR using the integer parameter assignments given in the slide presentation. The TkSlider component adjusts the RF input power level to the PA GainRF behavioral model.

WLAN_PA_cosim.dsn shows PA RFIC device level cosimulation at variable WLAN signal source data rates.

PowerAmp_sub has both a transistor-level RFIC static netlist and analog/RF behavioral models. You can activate the desired subnet, either behavioral or transistor netlist from Cadence RFIC.

Make sure you activate all of the components around the RFIC, especially the netlist include. On some PCs, it may be necessary to hard-set the path to the netlist, in the Networks folder. When the full RFIC is simulated, the VSA display updates very slowly.

WLAN_PA_fast_cosim.dsn is included only in the ADS 2002C version of the project. It shows PA RFIC device-level fast cosimulation at variable WLAN signal source data rates.

PA_sub_EVM_fast has the transistor-level RFIC static netlist only. With fast co-simulation, the VSA display updates very quickly.

WLAN_PA_esgc.dsn creates PA compression, phase noise, or multipath impairments and shows ESG4438C WLAN source connectivity (GPIB).

With this design, use the file wlan_WSGc_2GHz.set in \data for 89600 VSA demodulation. The default is no impairments. Activate the PA, mulipath blocks individually since they are in parallel, and delete the short.

For phase noise, deactivate "CleanLO" N_Tones, activate "NoisyLO" N_Tones.

ESG-C Link Registry Problems. On some new PCs, registry problems sometimes appear using the ADS2002 and ADS2002C ESG-C link. If you see an error "class not registered", do the following.

Open a DOS window. Change the directory (cd) to ADS2002\bin or ADS2002C\bin, and use dir *Esg*.dll to list all of the ESG files. One of these is EsgCom.dll. Use the command regsvr32 EsgCom.dll to register the file and fix the problem.

ADS Project Files: Analysis of a Sigma-Delta Modulator Using RF Behavioral Modeling and System Simulation